The present invention is generally related to the field of digital circuitry design and, more particularly, is related to a system and method for counting clock cycles in a digital circuit.
Many integrated circuits such as processor circuits, etc., employ one or more clocks that generate a steady stream of timing pulses to synchronize operation of the circuit itself. In many cases, a system clock signal of the integrated circuit is generated at a predetermined frequency using a phase locked loop. In general, for example, the clock rate of a computer identifies its overall processing speed and is often set to go as high as other components in the computer will allow.
Some processor circuits and other integrated circuits often include component circuits that require a clock signal that is synchronized with the system clock signal, but stepped down in frequency by a specific ratio in relation to the system clock speed. This ratio may vary from time to time during the operation of the overall circuit.
In order to step down a clock signal to a lower frequency, in some cases a clock counter circuit may be employed. These clock counter circuits may make use, for example, of a circuit resembling a bit shift register that comprises a number of registers or latches in a cascaded series. Each of these latches includes a clock input to receive the clock signal to be stepped down. The output of these latches are applied to a tri-state device. The outputs of the tri-state devices are applied to a common bus that is electrically coupled to a reset input on each of the latches.
A specific number of clock cycles is counted by shifting a logical value across the latches until one of them is reached with a corresponding selected tri-state device. The logical value (such as a logical xe2x80x9c1xe2x80x9d) is then placed on the common bus and resets all of the latches and is provided to state transition circuitry to trigger a change in the state of the stepped down clock. Thus, the system clock may be stepped down by any ratio depending upon the number of latches advancing the logical xe2x80x9c1xe2x80x9d before the selected tri-state device. However, with very high speed clocks, the above circuit is problematic in that the common bus can provide too great a capacitive load to be driven by a single selected tri-state device within the time frame necessary.
The present invention provides a system and method for counting a number of clock cycles to step down a clock signal to a lower frequency according to a desired ratio. Briefly described, in architecture, the system comprises a cascaded series of write latches and a cascaded series of erase latches. A cascaded series is defined herein as two or more latches stringed end-to-end with an output from a preceding latch applied as an input of the next adjacent latch. The output of each of the write latches is electrically coupled to a respective diverting multiplexer configured to divert a counting signal from the cascaded series of write latches to the cascaded series of erase latches.
Each diverting multiplexer applies one of either the output of a respective write latch or the output of a preceding adjacent erase latch to an input of a respective erase latch. Each of the diverting multiplexers receives a control input that determines which of its inputs is applies to the respective erase latch. A system clock whose cycles are to be counted on a repeated basis is applied to the clock inputs of the write latches and the erase latches. In order to count a specific number of cycles of the clock, a particular control input of one of the diverting multiplexers is set so as to divert a logical xe2x80x9c1xe2x80x9d advancing along the write latches into the erase latches. The specific number of clock cycles is counted by forcing a logical xe2x80x9c1xe2x80x9d to advance through a predetermined number of write and erase latches. Generally, the number of write and erase latches used to count a given number of clock cycles is even. Consequently, the present invention also includes an odd latch to enable the counting of an odd number of clock cycles.
The present system also provides for reset signal pathways by which the write latches are reset by the erase latches as a logical xe2x80x9c1xe2x80x9d is advanced along the cascaded series of erase latches. The reset signal pathways ensure that the write latches are reset to a logical xe2x80x9c0xe2x80x9d when the desired number of clock cycles has been counted so that the next group of clock cycles may be counted.
The above system is employed to count a desired number of clock cycles on a repeated basis, where the desired number of clock cycles counted depends upon the resulting clock frequency reduction ratio to be achieved. The present system generates an output each time the desired number of clock cycles is counted. This output may then be employed to change the state of a reduced clock signal accordingly.
The present invention can also be viewed as providing a method for counting a number of clock cycles. In this regard, the method can be broadly summarized by the following steps: counting a first number of the clock cycles by advancing a bit along a cascaded series of write latches, diverting the bit from the cascaded series of write latches into a cascaded series of erase latches, and counting a second number of the clock cycles by advancing the bit along the cascaded series of erase latches. The method further comprises the steps of counting a clock cycle in an odd latch coupled at an end of the cascaded series of erase latches, and, resetting the cascaded series of write latches while advancing the bit along the cascaded series of erase latches.
The system and method of the present invention are programmable to achieve any one of a number of clock frequency reduction ratios, thereby providing a significant advantage. In particular, by manipulating the control inputs to the diverting multiplexers, a desired number of write latches and erase latches may be employed to count the clock cycles on a repeated basis. In this manner, the user may specify a desired clock frequency reduction ratio with relative ease rather than requiring new and unique counting circuitry to accomplish different clock frequency reduction ratios.
Also, each erase latch need only reset a limited number of the write latches. In one embodiment, the number of write latches that is reset by each of the erase latches is two, although a greater or lesser number of write latches may be reset by each erase latch accordingly. This avoids the problem of employing a single common bus to reset all of the write latches and therefore, the clock counter circuit resulting therefrom will provide a reliable count of the clock cycles without the problem of the capacitive loading as experienced by the prior art.